基本信息:
- 专利标题: MEMORY MANAGEMENT UNIT FOR A NETWORK SWITCH
- 专利标题(中):网络交换机的存储器管理单元
- 申请号:PCT/US2000/011888 申请日:2000-06-22
- 公开(公告)号:WO01002965A3 公开(公告)日:2001-08-30
- 主分类号: H04L12/54
- IPC分类号: H04L12/54 ; H04L12/709 ; H04L12/803 ; H04L12/833 ; H04L12/851 ; H04L12/861 ; H04L12/931 ; H04L12/935 ; H04L29/06 ; H04L29/08 ; H04Q11/04 ; H04L12/56 ; G11C7/22
摘要:
A method and apparatus for storing data, the method including the steps of generating a glitchless fractional clock pulse in a circuit and transmitting the glitchless fractional clock pulse from the circuit to a data storage element. The data storage element thereafter stores data in the storage element upon receiving the glitchless fractional clock pulse. The apparatus for storing data includes at least one storage element having a data input, a storage enable input, and a data output, and at least one logic circuit having an activating input, a clock input, and a logic output. The at least one logic circuit generates a glitchless fractional clock pulse on the logic output, wherein the logic output is connected to the storage enable input of the storage element and operating to enable the at least one storage element to store data resident on the data input at an optimally stable time.
摘要(中):
一种用于存储数据的方法和设备包括在电路中生成无瞬态分数时钟脉冲并将其从电路传送到数据存储元件,数据存储元件在接收时存储它。 该数据存储设备包括:至少一个存储元件,包括数据输入,存储使能输入,数据输出; 以及包括使能输入,时钟输入,逻辑输入和逻辑输出的至少一个逻辑电路。 逻辑电路在连接到存储元件的存储启用输入端的逻辑输出端上创建瞬态无关的分数时钟脉冲,其允许存储元件存储存储在存储元件上的数据。 数据录入在最佳稳定时间。