基本信息:
- 专利标题： CLOCK SKEW-ADJUSTABLE CHIP CLOCK ARCHITECTURE OF PROGARMMABLE LOGIC CHIP
- 申请号：US17955581 申请日：2022-09-29
- 公开(公告)号：US20230016311A1 公开(公告)日：2023-01-19
- 发明人： Chenguang KUANG , Yanfei ZHANG , Boyin CHEN , Jicong FAN
- 申请人： WUXI ESIONTECH CO., LTD.
- 申请人地址： CN Wuxi
- 专利权人： WUXI ESIONTECH CO., LTD.
- 当前专利权人： WUXI ESIONTECH CO., LTD.
- 当前专利权人地址： CN Wuxi
- 优先权： CN202111470014.6 20211203
- 主分类号： G06F1/08
- IPC分类号： G06F1/08 ; G06F1/10 ; G06F30/396
摘要：
A delay adjustment cell is disposed in a channel of at least one regional clock of a chip clock architecture, and the delay adjustment cell includes a plurality of parallel delay paths with different delay values. The delay adjustment cell gates one of the delay paths based on an obtained configuration signal such that a connected regional clock has a corresponding target delay, and a target delay of each regional clock corresponds to a clock skew mode of the programmable logic chip. A clock skew between different regional clocks is adjusted by controlling the gated delay path in the delay adjustment cell, such that a clock skew of the chip can be adjusted in a relatively large range. Under the same resource configuration, different path choices of the delay adjustment cell lead to different clock skews to meet different clock skew modes in different application scenarios.