![MANAGING INTEGRITY OF FRAMED PAYLOADS USING REDUNDANT SIGNALS](/abs-image/US/2019/02/14/US20190052402A1/abs.jpg.150x150.jpg)
基本信息:
- 专利标题: MANAGING INTEGRITY OF FRAMED PAYLOADS USING REDUNDANT SIGNALS
- 申请号:US16162283 申请日:2018-10-16
- 公开(公告)号:US20190052402A1 公开(公告)日:2019-02-14
- 发明人: Sergio Licardie , Rishipal Arya , Robert Brown
- 申请人: Aviat U.S., Inc.
- 申请人地址: US CA Milpitas
- 专利权人: Aviat U.S., Inc.
- 当前专利权人: Aviat U.S., Inc.
- 当前专利权人地址: US CA Milpitas
- 主分类号: H04L1/00
- IPC分类号: H04L1/00 ; H03M13/47 ; H04B7/08 ; H03M13/37 ; H04L1/02 ; H04B7/10
摘要:
A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network.
公开/授权文献:
IPC结构图谱:
H | 电学 |
--H04 | 电通信技术 |
----H04L | 数字信息的传输,例如电报通信 |
------H04L1/00 | 检测或防止收到信息中的差错的装置 |