发明申请
US20180012812A1 HETEROGENEOUS INTEGRATION OF 3D SI AND III-V VERTICAL NANOWIRE STRUCTURES FOR MIXED SIGNAL CIRCUITS FABRICATION
审中-公开
基本信息:
- 专利标题： HETEROGENEOUS INTEGRATION OF 3D SI AND III-V VERTICAL NANOWIRE STRUCTURES FOR MIXED SIGNAL CIRCUITS FABRICATION
- 申请号：US15667305 申请日：2017-08-02
- 公开(公告)号：US20180012812A1 公开(公告)日：2018-01-11
- 发明人： Suraj Kumar PATIL , Ajey P. JACOB
- 申请人： GLOBALFOUNDRIES Inc.
- 主分类号： H01L21/8238
- IPC分类号： H01L21/8238 ; H01L27/092 ; H01L29/06 ; H01L21/02 ; H01L29/786 ; H01L29/423
摘要：
A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or SixGe1-x substrate; forming a conformal SiN, SiOxCyNz layer over side and bottom surfaces of the first trenches; filling the first trenches with SiOx; forming a first mask over portions of the Si, Ge, III-V, or SixGe1-x substrate; removing exposed portions of the Si, Ge, III-V, or SixGe1-x substrate, forming second trenches; forming III-V, III-VxMy, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-V, III-VxMy, or Si nanowires and intervening first trenches; removing the SiOx layer, forming third trenches; and removing the second mask.
公开/授权文献:
IPC结构图谱:
| H | 电学 |
| --H01 | 基本电气元件 |
| ----H01L | 半导体器件；其他类目未包含的电固体器件 |
| ------H01L21/00 | 专门适用于制造或处理半导体或固体器件或其部件的方法或设备 |
| --------H01L21/67 | .专门适用于在制造或处理过程中处理半导体或电固体器件的装置；专门适合于在半导体或电固体器件或部件的制造或处理过程中处理晶片的装置 |
| ----------H01L21/71 | ..限定在组H01L21/70中的器件的特殊部件的制造 |
| ------------H01L21/78 | ...把衬底连续地分成多个独立的器件 |
| --------------H01L21/782 | ....制造多个器件，每一个由单个电路元件组成 |
| ----------------H01L21/822 | .....衬底是采用硅工艺的半导体的 |
| ------------------H01L21/8222 | ......双极工艺 |
| --------------------H01L21/8234 | .......MIS工艺 |
| ----------------------H01L21/8238 | ........互补场效应晶体管，例如CMOS |