
基本信息:
- 专利标题: PARALLEL BIT LINE THREE-DIMENSIONAL RESISTIVE RANDOM ACCESS MEMORY
- 专利标题(中):并行线三维电阻随机存取存储器
- 申请号:US14635419 申请日:2015-03-02
- 公开(公告)号:US20160260775A1 公开(公告)日:2016-09-08
- 发明人: Seje TAKAKI
- 申请人: SANDISK 3D LLC
- 主分类号: H01L27/24
- IPC分类号: H01L27/24 ; H01L45/00 ; G11C13/00
摘要:
Resistive random access memory (ReRAM) array includes line stack structures located over a substrate. The line stack structures are laterally spaced apart along a first horizontal direction, and extend along a second horizontal direction that is different from the first horizontal direction. Each line stack structure comprises an alternating plurality of word lines and bit lines. An intervening line stack including a memory material line structure, an intrinsic semiconductor material line structure, and a doped semiconductor material line structure is located between each vertically neighboring pair of a word line and a bit line within the alternating plurality of word lines and bit lines. A two-dimensional array of vertical selector lines functions as gate electrodes that activates a semiconductor channel between a word line and a bit line. Resistance of the memory material line structure contacting the activated semiconductor channel can be programmed and/or measured within the ReRAM array.
摘要(中):
电阻随机存取存储器(ReRAM)阵列包括位于衬底上的线堆栈结构。 线堆叠结构沿着第一水平方向横向间隔开,并且沿着与第一水平方向不同的第二水平方向延伸。 每个线堆叠结构包括交替的多个字线和位线。 包括存储材料线结构,本征半导体材料线结构和掺杂半导体材料线结构的插入线堆叠位于交替的多个字线和位线之间的字线和位线的每个垂直相邻对之间 。 垂直选择器线的二维阵列用作激活字线和位线之间的半导体通道的栅电极。 可以在ReRAM阵列内编程和/或测量与激活的半导体通道接触的记忆材料线结构的电阻。
公开/授权文献:
IPC结构图谱:
H | 电学 |
--H01 | 基本电气元件 |
----H01L | 半导体器件;其他类目未包含的电固体器件 |
------H01L27/00 | 由在一个共用衬底内或其上形成的多个半导体或其他固态组件组成的器件 |
--------H01L27/24 | .包括无电位跃变势垒或表面势垒的用于整流、放大,或切换的固态组件的 |