
基本信息:
- 专利标题: RECEIVING DEVICE AND RECEIVING PROCESS METHOD
- 专利标题(中):接收设备和接收过程方法
- 申请号:US14794200 申请日:2015-07-08
- 公开(公告)号:US20160065266A1 公开(公告)日:2016-03-03
- 发明人: Tsuyoshi Hasegawa
- 申请人: FUJITSU LIMITED
- 优先权: JP2014-175458 20140829
- 主分类号: H04B1/7103
- IPC分类号: H04B1/7103 ; H04L1/06
摘要:
A communication processor in a receiving device includes a chip equalizer, a correction matrix calculating unit, and a correction unit. The chip equalizer equalizes a plurality of reception signal sequences received via an antenna. The correction matrix calculating unit calculates a correction matrix by using a channel matrix, a weight of an equalizer, a power ratio of a pilot signal to a reception signal, a number of multi codes, and a spreading factor of the reception signal sequences. The correction unit corrects, by using the correction matrix, the reception signal sequences equalized by the chip equalizer.
摘要(中):
接收装置中的通信处理器包括码片均衡器,校正矩阵计算单元和校正单元。 码片均衡器对通过天线接收的多个接收信号序列进行均衡。 校正矩阵计算单元通过使用信道矩阵,均衡器的权重,导频信号与接收信号的功率比,多个码的数量和接收信号序列的扩展因子来计算校正矩阵。 校正单元通过使用校正矩阵校正由码片均衡器均衡的接收信号序列。
公开/授权文献:
- US09525456B2 Receiving device and receiving process method 公开/授权日:2016-12-20
IPC结构图谱:
H | 电学 |
--H04 | 电通信技术 |
----H04B | 传输 |
------H04B1/00 | 不包含在H04B3/00至H04B13/00单个组中的传输系统的部件;不以所使用的传输媒介为特征区分的传输系统的部件 |
--------H04B1/69 | .一般扩频技术 |
----------H04B1/707 | ..利用直接序列调制的 |
------------H04B1/7073 | ...同步方面 |
--------------H04B1/7103 | ....干扰为多址接入干扰 |