At least one semiconductor fin is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor fin. The amount of the etched portions of the insulator is selected such that a metallic gate electrode layer fills the entire gap between the recessed surfaces of the insulator layer and the bottom surface(s) of the at least one semiconductor fin. An interface between the metallic gate electrode layer and a semiconductor gate electrode layer contiguously extends over the at least one semiconductor fin and does not underlie any of the at least one semiconductor fin. During patterning of a gate electrode, removal of the semiconductor material in the semiconductor gate electrode layer can be facilitated because the semiconductor gate electrode layer is not present under the at least one semiconductor fin.