基本信息:
- 专利标题： Semiconductor Device and Manufacturing Method Thereof
- 专利标题（中）：半导体器件及其制造方法
- 申请号：US14354091 申请日：2011-10-31
- 公开(公告)号：US20140252576A1 公开(公告)日：2014-09-11
- 发明人： Hisashi Tanie , Hiroshi Shintani , Naotaka Tanaka
- 申请人： Hisashi Tanie , Hiroshi Shintani , Naotaka Tanaka
- 申请人地址： JP Chiyoda-ku, Tokyo
- 专利权人： Hitachi, Ltd.
- 当前专利权人： Hitachi, Ltd.
- 当前专利权人地址： JP Chiyoda-ku, Tokyo
- 国际申请： PCT/JP2011/075073 WO 20111031
- 主分类号： H01L23/00
- IPC分类号： H01L23/00 ; H01L21/52
摘要：
A semiconductor device has a packaging structure in which a top surface of a semiconductor chip 1 is electrically connected to a conductive member 4 through a deformation absorption layer 2a and a joining layer 3a and a bottom surface thereof is electrically connected to a conductive member 5 through a deformation absorption layer 2b and a joining layer 3b. Each of the deformation absorption layers 2a and 2b includes a nano-structure layer 7 arranged at a center of a thickness direction and plate layers 6 and 8 of two layers with the nano-structure layer 7 therebetween. The nano-structure layer 7 has a structure in which a plurality of nano-structures 9 having a size of 1 μm or less are two-dimensionally arranged and thermal stress due to a thermal deformation difference of each member forming the semiconductor device is absorbed by deformation of the nano-structures 9.
摘要（中）：
半导体器件具有封装结构，其中半导体芯片1的顶表面通过变形吸收层2a和接合层3a电连接到导电构件4，并且其底表面通过导电构件5电连接到导电构件5 变形吸收层2b和接合层3b。 每个变形吸收层2a和2b包括布置在厚度方向中心的纳米结构层7和两层的层6和8，其间具有纳米结构层7。 纳米结构层7具有二维排列多个尺寸为1μm以下的纳米结构体9的结构，并且由于形成半导体器件的各构件的热变形差导致的热应力被 纳米结构变形9。
IPC结构图谱:
| H | 电学 |
| --H01 | 基本电气元件 |
| ----H01L | 半导体器件；其他类目未包含的电固体器件 |
| ------H01L23/00 | 半导体或其他固态器件的零部件 |