
基本信息:
- 专利标题: MEMORY APPARATUS
- 专利标题(中):记忆装置
- 申请号:US13584393 申请日:2012-08-13
- 公开(公告)号:US20130326184A1 公开(公告)日:2013-12-05
- 发明人: Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo
- 申请人: Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo
- 申请人地址: TW Hsinchu
- 专利权人: MACRONIX INTERNATIONAL CO., LTD.
- 当前专利权人: MACRONIX INTERNATIONAL CO., LTD.
- 当前专利权人地址: TW Hsinchu
- 主分类号: G06F12/00
- IPC分类号: G06F12/00
摘要:
A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.
摘要(中):
存储装置包括主机装置和从装置。 主机设备存储验证数据。 从设备包括存储器单元,控制单元和逻辑单元。 控制单元驱动存储单元以在数据传输子时段中提供存储数据,并且还在虚拟子周期中提供指示第一验证数据的控制信号。 逻辑单元响应于第一控制信号,在虚拟子周期中提供与验证数据基本上相同的数据值的第一前同步码数据。 前导码数据和存储数据根据内部时钟信号发送。 主机设备根据外部时钟信号对第一前同步码数据进行采样,并且通过比较第一前导码数据和第一验证数据来确定外部和内部时钟信号是否被同步。
公开/授权文献:
- US08825978B2 Memory apparatus 公开/授权日:2014-09-02