基本信息:
- 专利标题： SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
- 专利标题（中）：半导体器件及其制造方法
- 申请号：US13534078 申请日：2012-06-27
- 公开(公告)号：US20130001804A1 公开(公告)日：2013-01-03
- 发明人： YOSHIHIKO SHIMANUKI , Yoshihiro Suzuki , Koji Tsuchiya
- 申请人： YOSHIHIKO SHIMANUKI , Yoshihiro Suzuki , Koji Tsuchiya
- 专利权人： RENESAS ELECTRONICS CORPORATION
- 当前专利权人： RENESAS ELECTRONICS CORPORATION
- 优先权： JP2002-191666 20020701
- 主分类号： H01L23/48
- IPC分类号： H01L23/48
摘要：
There are constituted by a tab on which a semiconductor chip is mounted, a sealing portion formed by resin-sealing the semiconductor chip, a plurality of leads each having a mounted surface exposed to a peripheral portion of a rear surface of the sealing portion and a sealing-portion forming surface disposed on an opposite side thereto, and a wire for connecting a pad of the semiconductor chip and a lead, wherein the length between inner ends of the sealing-portion forming surfaces of the leads disposed so as to oppose to each other is formed to be larger than the length between inner ends of the mounted surfaces. Thereby, a chip mounting region surrounded by the inner end of the sealing-portion forming surface of each lead can be expanded and the size of the mountable chip is increased.
摘要（中）：
由安装半导体芯片的突片，通过树脂密封半导体芯片形成的密封部分，多个引线，每个引线具有暴露于密封部分的后表面的周边部分的安装表面，以及 密封部分形成表面设置在其相对侧上，以及导线，用于连接半导体芯片的焊盘和引线，其中引线的密封部分形成表面的内端之间的长度设置为与每个 另一个形成为大于安装表面的内端之间的长度。 由此，能够扩大由各引线的密封部形成面的内端包围的芯片安装区域，能够增大安装芯片的尺寸。
公开/授权文献:
- US08390133B2 Semiconductor device and manufacturing method thereof 公开/授权日：2013-03-05
IPC结构图谱:
| H | 电学 |
| --H01 | 基本电气元件 |
| ----H01L | 半导体器件；其他类目未包含的电固体器件 |
| ------H01L23/00 | 半导体或其他固态器件的零部件 |
| --------H01L23/48 | .用于向或自处于工作中的固态物体通电的装置，例如引线、接线端装置 |