基本信息:
- 专利标题： ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREFOR
- 专利标题（中）：电子设备及其制造方法
- 申请号：US13106933 申请日：2011-05-13
- 公开(公告)号：US20110284912A1 公开(公告)日：2011-11-24
- 发明人： Shigenobu Sekine , Yurina Sekine , Yoshiharu Kuwana
- 申请人： Shigenobu Sekine , Yurina Sekine , Yoshiharu Kuwana
- 申请人地址： JP Tokyo
- 专利权人： NAPRA CO., LTD.
- 当前专利权人： NAPRA CO., LTD.
- 当前专利权人地址： JP Tokyo
- 优先权： JP2010-117008 20100521; JP2011-056556 20110315
- 主分类号： H01L33/62
- IPC分类号： H01L33/62 ; H01L21/28
摘要：
An electronic device includes a semiconductor substrate, an insulating material-filled layer and a vertical conductor. The semiconductor substrate has a vertical hole extending in a thickness direction thereof. The insulating material-filled layer is a ring-shaped layer filled in the vertical hole for covering an inner periphery thereof and includes an organic insulating material or an inorganic insulating material mainly of a glass and a nanocomposite ceramic. The nanocomposite ceramic has a specific resistance of greater than 1014 Ω·cm at room temperature and a relative permittivity of 4 to 9. The vertical conductor is a solidified metal body filled in an area surrounded by the insulating material-filled layer.
摘要（中）：
电子设备包括半导体衬底，绝缘材料填充层和垂直导体。 半导体衬底具有沿其厚度方向延伸的垂直孔。 绝缘材料填充层是填充在用于覆盖其内周的垂直孔中的环状层，并且包括主要由玻璃和纳米复合陶瓷组成的有机绝缘材料或无机绝缘材料。 纳米复合陶瓷在室温下的电阻率大于1014＆OHgr·cm，相对介电常数为4〜9。垂直导体是填充在被绝缘材料填充层包围的区域中的凝固金属体。
公开/授权文献:
- US09685394B2 Electronic device and manufacturing method therefor 公开/授权日：2017-06-20