发明申请
US20090262475A1 METHOD AND SYSTEM FOR MITIGATING RISK OF ELECTROSTATIC DISCHARGE FOR A SYSTEM ON CHIP (SOC)
有权
基本信息:
- 专利标题： METHOD AND SYSTEM FOR MITIGATING RISK OF ELECTROSTATIC DISCHARGE FOR A SYSTEM ON CHIP (SOC)
- 专利标题（中）：用于减少芯片系统（SOC）的静电放电风险的方法和系统
- 申请号：US12265601 申请日：2008-11-05
- 公开(公告)号：US20090262475A1 公开(公告)日：2009-10-22
- 发明人： Hooman Darabi , Ming Wang Sze , Kent Oertle , Paul Chang
- 申请人： Hooman Darabi , Ming Wang Sze , Kent Oertle , Paul Chang
- 主分类号： H02H9/04
- IPC分类号： H02H9/04
摘要：
Aspects of a method and system for mitigating risk of electrostatic discharge in a system on chip are provided. In this regard, for an IC comprising a plurality of portions electrically isolated from one another within the IC, ESD current may be routed via one or more paths within and/or on a package to which the IC is bonded. The one or more paths may electrically couple two or more of the portions of the IC. The one or more paths may have low impedance at DC and high impedance at one or more frequencies utilized in the integrated circuit. One of the portions of the IC may be a ground plane for RF circuitry. One of the portions of the IC may be a ground plane for digital circuitry. The one or more paths may be fabricated in one or more metal layers of said package.
摘要（中）：
提供了一种降低片上系统中静电放电风险的方法和系统。 在这方面，对于包括在IC内彼此电隔离的多个部分的IC，ESD电流可以经由与IC结合的封装内和/或上的一个或多个路径布线。 一个或多个路径可以电耦合IC的两个或多个部分。 一个或多个路径在集成电路中使用的一个或多个频率处的DC处可具有低阻抗和高阻抗。 IC的一部分可以是用于RF电路的接地平面。 IC的部分之一可以是用于数字电路的接地平面。 一个或多个路径可以在所述包装的一个或多个金属层中制造。