基本信息:
- 专利标题： THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
- 专利标题（中）：薄膜晶体管阵列及其制造方法
- 申请号：US11619451 申请日：2007-01-03
- 公开(公告)号：US20070102770A1 公开(公告)日：2007-05-10
- 发明人： Woo-Geun Lee , Beom-Seok Cho , Je-Hun Lee , Chang-Oh Jeong , Sang-Gab Kim , Min-Seok Oh , Young-Wook Lee , Hee-Hwan Choe
- 申请人： Woo-Geun Lee , Beom-Seok Cho , Je-Hun Lee , Chang-Oh Jeong , Sang-Gab Kim , Min-Seok Oh , Young-Wook Lee , Hee-Hwan Choe
- 优先权： KR10-2004-0018805 20040319; KR10-2004-0064021 20040813
- 主分类号： H01L29/76
- IPC分类号： H01L29/76
摘要：
A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.
摘要（中）：
一种制造薄膜晶体管阵列面板的方法，包括在衬底上形成栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在半导体上形成数据线和漏电极 在所述数据线和所述漏电极上沉积钝化层，在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂，使用所述光致抗蚀剂作为掩模蚀刻所述钝化层 露出漏极的一部分，去除光致抗蚀剂的第二部分，沉积导电膜，以及去除光致抗蚀剂的第一部分，以在漏电极的暴露部分上形成像素电极。