基本信息:
- 专利标题： Low power memory sub-system architecture
- 申请号：US11198563 申请日：2005-08-05
- 公开(公告)号：US20070030750A1 公开(公告)日：2007-02-08
- 发明人： Sho-Mo Chen , Fei Ye , Feng Yang
- 申请人： Sho-Mo Chen , Fei Ye , Feng Yang
- 申请人地址： US CA Cupertino
- 专利权人： ForteMedia, Inc.
- 当前专利权人： ForteMedia, Inc.
- 当前专利权人地址： US CA Cupertino
- 主分类号： G11C5/14
- IPC分类号： G11C5/14
摘要：
Disclosed methods and apparatus provide embedded memory architectures that lower the overall operational power consumption of memory arrays without sacrificing memory access speed. Because in large memory arrays the leakage current is a considerable portion of the overall power consumption, leakage reduction in memory arrays, manufactured by advanced processing technologies, is a major challenge. To reduce leakage, methods and apparatus are presented for memory access and for power- and ground-supply monitoring and management at memory sub-array level.
公开/授权文献:
- US07209404B2 Low power memory sub-system architecture 公开/授权日：2007-04-24