基本信息:
- 专利标题： Master controller architecture
- 专利标题（中）：主控制器架构
- 申请号：US10999720 申请日：2004-11-30
- 公开(公告)号：US20060129874A1 公开(公告)日：2006-06-15
- 发明人： Alexandre Andreev , Sergey Gribok , Anatoli Bolotov
- 申请人： Alexandre Andreev , Sergey Gribok , Anatoli Bolotov
- 主分类号： G06F11/00
- IPC分类号： G06F11/00
摘要：
A master controller for an RRAM subsystem. An interface communicates with at least one RRAM controller. A main control unit selects and implements test and repair operations on the RRAM subsystem through the RRAM controller. A timer determines a maximum number of test and repair operations that can be implemented within a given time. Thus, a master controller is included in the RRAM subsystem. The master controller has a relatively simple interface, and performs test and repair operations on the RRAM subsystem. The advantages of using the master controller include an elimination of additional test ports, simplification of the process of preparing the test vectors for RRAM testing, and the master controller is able to accumulate test results and initiate repairs based on those results. In this manner, the RRAM subsystem has a self-repair functionality.
摘要（中）：
用于RRAM子系统的主控制器。 接口与至少一个RRAM控制器通信。 主控单元通过RRAM控制器对RRAM子系统进行测试和修复操作。 定时器确定在给定时间内可以实现的最大测试和修复操作数。 因此，主控制器包含在RRAM子系统中。 主控制器具有相对简单的接口，并对RRAM子系统执行测试和修复操作。 使用主控制器的优点包括消除额外的测试端口，简化了用于RRAM测试的测试向量的准备过程，并且主控制器能够根据这些结果积累测试结果并启动修复。 以这种方式，RRAM子系统具有自修复功能。
公开/授权文献:
- US07308633B2 Master controller architecture 公开/授权日：2007-12-11