基本信息:
- 专利标题： Interconnect module with reduced power distribution impedance
- 专利标题（中）：互连模块具有降低的配电阻抗
- 申请号：US10199926 申请日：2002-07-19
- 公开(公告)号：US20040170006A9 公开(公告)日：2004-09-02
- 发明人： Mark F. Sylvester , David A. Hanson , William G. Petefish
- 主分类号： H05K007/02
- IPC分类号： H05K007/02
摘要：
An interconnect module for an integrated circuit chip incorporates a thin, high dielectric constant embedded capacitor structure to provide reduced power distribution impedance, and thereby promote higher frequency operation. The interconnect module is capable of reliably attaching an integrated circuit chip to a printed wiring board via solder ball connections, while providing reduced power distribution impedance of less than or equal to approximately 0.60 ohms at operating frequencies in excess of 1.0 gigahertz.
摘要（中）：
用于集成电路芯片的互连模块结合了薄的高介电常数嵌入式电容器结构，以提供降低的功率分布阻抗，从而促进更高频率的操作。 互连模块能够通过焊球连接将集成电路芯片可靠地附接到印刷线路板，同时在超过1.0千兆赫的工作频率下提供小于或等于约0.60欧姆的降低的功率分布阻抗。