基本信息:
- 专利标题： Assemblies having stacked semiconductor chips and methods of making same
- 专利标题（中）：堆叠半导体芯片的组件及其制造方法
- 申请号：US10611390 申请日：2003-07-01
- 公开(公告)号：US20040108581A1 公开(公告)日：2004-06-10
- 发明人： Delin Li
- 申请人： Tessera, Inc.
- 申请人地址： CA San Jose
- 专利权人： Tessera, Inc.
- 当前专利权人： Tessera, Inc.
- 当前专利权人地址： CA San Jose
- 主分类号： H01L023/02
- IPC分类号： H01L023/02
摘要：
A method of manufacturing a plurality of semiconductor chip packages and the resulting chip package assemblies. The method includes providing a circuitized substrate having terminals and leads. A first microelectronic element is arranged with the substrate and contacts on the microelectronic element are connected to the substrate. A conductive member is placed on top of the first microelectronic element and is used to support a second microelectronic element. The second microelectronic element is arranged with the conductive member in a top and bottom position. The second microelectronic element is then also connected by leads from contacts on the second microelectronic element to pads and terminals on the circuitized substrate. The conductive member is then connected to a third pad or set of pads on the substrate. An encapsulant material may be deposited so as to encapsulate the leads and at least one surface of the microelectronic elements. The encapsulant material is then cured thereby defining a composite of chip assemblies which may be singulated into individual chip packages.
摘要（中）：
一种制造多个半导体芯片封装的方法以及所得到的芯片封装组件。 该方法包括提供具有端子和引线的电路化基板。 第一微电子元件与衬底一起布置，微电子元件上的触点连接到衬底。 导电构件放置在第一微电子元件的顶部上，并用于支撑第二微电子元件。 第二微电子元件布置成导电构件处于顶部和底部位置。 第二微电子元件然后还通过引线从第二微电子元件上的触点连接到电路化基板上的焊盘和端子。 然后将导电构件连接到衬底上的第三衬垫或一组衬垫。 可以沉积密封剂材料以便封装引线和微电子元件的至少一个表面。 密封剂材料然后被固化，从而限定了可以被分成单个芯片封装的芯片组件的复合材料。