基本信息:
- 专利标题: 具有高產能之超高選擇性多晶矽蝕刻
- 专利标题(英):Ultrahigh selective polysilicon etch with high throughput
- 专利标题(中):具有高产能之超高选择性多晶硅蚀刻
- 申请号:TW105136072 申请日:2016-11-07
- 公开(公告)号:TW201730966A 公开(公告)日:2017-09-01
- 发明人: 楊 登亮 , YANG, DENGLIANG , 伊森 夸梅 , EASON, KWAME , 雅各布 費薩爾 , YAQOOB, FAISAL , 朴准弘 , PARK, JOON HONG
- 申请人: 諾發系統有限公司 , NOVELLUS SYSTEMS, INC.
- 专利权人: 諾發系統有限公司,NOVELLUS SYSTEMS, INC.
- 当前专利权人: 諾發系統有限公司,NOVELLUS SYSTEMS, INC.
- 代理人: 周良謀; 周良吉
- 优先权: 14/938,635 20151111
- 主分类号: H01L21/3213
- IPC分类号: H01L21/3213 ; H01L21/67 ; H01L29/66 ; H01L21/683 ; H01J37/32 ; H01L21/02
Provided are methods and apparatuses for removing a polysilicon layer on a wafer, where the wafer can include a nitride layer, a low-k dielectric layer, an oxide layer, and other films. A plasma of a hydrogen-based species and a fluorine-based species is generated in a remote plasma source, and the wafer is exposed to the plasma at a relatively low temperature to limit the formation of solid byproduct. In some implementations, the wafer is maintained at a temperature below about 60 DEG C. The polysilicon layer is removed at a very high etch rate, and the selectivity of polysilicon over the nitride layer and the oxide layer is very high. In some implementations, the wafer is supported on a wafer support having a plurality of thermal zones configured to define a plurality of different temperatures across the wafer.
信息查询:
EspacenetIPC结构图谱:
H | 电学 |
--H01 | 基本电气元件 |
----H01L | 半导体器件;其他类目未包含的电固体器件 |
------H01L21/00 | 专门适用于制造或处理半导体或固体器件或其部件的方法或设备 |
--------H01L21/02 | .半导体器件或其部件的制造或处理 |
----------H01L21/027 | ..未在H01L21/18或H01L21/34组中包含的为进一步的光刻工艺在半导体之上制作掩膜 |
------------H01L21/18 | ...器件有由周期表第Ⅳ族元素或含有/不含有杂质的AⅢBⅤ族化合物构成的半导体,如掺杂材料 |
--------------H01L21/26 | ....用波或粒子辐射轰击的 |
----------------H01L21/302 | .....改变半导体材料的表面物理特性或形状的,例如腐蚀、抛光、切割 |
------------------H01L21/3205 | ......非绝缘层的沉积,例如绝缘层上的导电层、电阻层(器件内部的通电装置入H01L23/52);这些层的后处理 |
--------------------H01L21/321 | .......后处理 |
----------------------H01L21/3213 | ........对该层进行物理的或化学的腐蚀,例如由预沉积的外延层产生一个形成图形的层 |