The present invention proposes a semiconductor integrated circuit device manufacturing method in which by allowing a logic gate forming layer (25) provided at the periphery of a memory gate (10) to remain as is, to that extent, the generation of a reaction gas which arises due to dry etching when the logic gate forming layer (25) is dry etched becomes easier, and as a result thereof, it becomes possible to remove the logic gate forming layer (25) using an automatic stopping point detection method for determining the etching amount with changes in the reaction gas serving as a reference, and the logic gate forming layer (25) in a memory circuit region (ER1) can be removed more accurately. As a result of the foregoing, over etching of a memory circuit region insulation layer (6a) can be controlled when removing the logic gate forming layer (25) in the memory circuit region (ER1), and because the logic gate forming layer (25) in the memory circuit region (ER1) has already been removed when forming a logic gate (15, 18 (fig. 6)), it is possible to prevent an unwanted state in which the logic gate forming layer (25) remains in the memory circuit region (ER1) when forming the logic gate (15, 18).