基本信息:
- 专利标题： 延遲線電路及其延遲方法
- 专利标题（英）：Delay line circuit and delay method thereof
- 专利标题（中）：延迟线电路及其延迟方法
- 申请号：TW103145543 申请日：2014-12-25
- 公开(公告)号：TW201539984A 公开(公告)日：2015-10-16
- 发明人： 黃明杰 , HUANG, MINGCHIEH , 陳建宏 , CHERN, CHANHONG , 黃琮靖 , HUANG, TSUNGCHING , 林志昌 , LIN, CHIHCHANG , 薛福隆 , HSUEH, FULUNG
- 申请人： 台灣積體電路製造股份有限公司 , TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- 申请人地址： 新竹市
- 专利权人： 台灣積體電路製造股份有限公司,TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- 当前专利权人： 台灣積體電路製造股份有限公司,TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- 当前专利权人地址： 新竹市
- 代理人： 蔡坤財; 李世章
- 优先权： 14/187,951 20140224
- 主分类号： H03K5/14
- IPC分类号： H03K5/14
A delay line circuit comprises a plurality of delay units configured to receive an input signal and modify the input signal to produce a first output signal. The delay line circuit also comprises a variable delay line unit that comprises an input end configured to receive the first output signal; an output end configured to output a second output signal; a first line between the input end and the output end, the first line comprising, in series, a first inverter, a second inverter, a first speed control unit, and a third inverter; a second line between the input end and the output end, the second line comprising, in series, a fourth inverter, a second speed control unit, a fifth inverter, and a sixth inverter. The delay line circuit is also configured to selectively transmit the received first output signal through one of the first line or the second line.
公开/授权文献:
- TWI544748B 延遲線電路及其延遲方法 公开/授权日：2016-08-01