基本信息:
- 专利标题： 可重組態延遲電路、及使用其延遲電路之延遲監視電路、偏差修正電路、偏差測定方法及偏差修正方法
- 专利标题（英）：Reconfigurable delay circuit, delay monitor circuit using said delay circuit, variation correction circuit, variation measurement method, and variation correction method
- 专利标题（中）：可重组态延迟电路、及使用其延迟电路之延迟监视电路、偏差修正电路、偏差测定方法及偏差修正方法
- 申请号：TW103126689 申请日：2014-08-05
- 公开(公告)号：TW201526547A 公开(公告)日：2015-07-01
- 发明人： 小野寺秀俊 , ONODERA, HIDETOSHI , A K M 瑪弗茲魯 伊斯蘭 , A. K. M MAHFUZUL, ISLAM
- 申请人： 獨立行政法人科學技術振興機構 , JAPAN SCIENCE AND TECHNOLOGY AGENCY
- 专利权人： 獨立行政法人科學技術振興機構,JAPAN SCIENCE AND TECHNOLOGY AGENCY
- 当前专利权人： 獨立行政法人科學技術振興機構,JAPAN SCIENCE AND TECHNOLOGY AGENCY
- 代理人： 丁國隆
- 优先权： 2013-169965 20130819
- 主分类号： H03K5/134
- IPC分类号： H03K5/134 ; G01R31/28
A delay circuit (10) containing a first inverting circuit, which contains a pull-up circuit (2) and a pull-down circuit (3), and a second inverting circuit, which contains a pull-up circuit (4) and a pull-down circuit (5). The delay circuit also contains: a first pass transistor (6) connected in series to the pull-up circuit of the first inverting circuit between a power supply potential and an output node; a second pass transistor (7) connected in series to the pull-down circuit (2) of the first inverting circuit between a ground potential and the output node (Out); a third pass transistor (8) inserted in series between an input node (In) and the pull-up circuit of the second inverting circuit; and a fourth pass transistor (9) inserted in series between the input node and the pull-down circuit of the second inverting circuit. The delay characteristic of the delay circuit is changed by a combination of control signals (C1-C4) applied to the gates of the first - fourth pass transistors.
公开/授权文献:
- TWI548221B 可重組態延遲電路、及使用其延遲電路之延遲監視電路、偏差修正電路、偏差測定方法及偏差修正方法 公开/授权日：2016-09-01
信息查询:
EspacenetIPC结构图谱:
| H | 电学 |
| --H03 | 基本电子电路 |
| ----H03K | 脉冲技术 |
| ------H03K5/00 | 本小类中一个其他大组不包含的脉冲处理 |
| --------H03K5/003 | .变更直流电平 |
| ----------H03K5/133 | ..用有源延时装置链的 |
| ------------H03K5/134 | ...用场效应晶体管的 |