发明专利
TW200814246A 晶片封裝體、堆疊型晶片封裝結構及其製造方法 CHIP PACKAGE, STACKED CHIP PACKAGE STRUCTURE AND MANUFACTURE METHOD OF THE SAME
审中-公开
基本信息:
- 专利标题： 晶片封裝體、堆疊型晶片封裝結構及其製造方法 CHIP PACKAGE, STACKED CHIP PACKAGE STRUCTURE AND MANUFACTURE METHOD OF THE SAME
- 专利标题（英）：Chip package, stacked chip package structure and manufacture method of the same
- 专利标题（中）：芯片封装体、堆栈型芯片封装结构及其制造方法 CHIP PACKAGE, STACKED CHIP PACKAGE STRUCTURE AND MANUFACTURE METHOD OF THE SAME
- 申请号：TW095133602 申请日：2006-09-12
- 公开(公告)号：TW200814246A 公开(公告)日：2008-03-16
- 发明人： 莊孟融 CHUANG, MENG JUNG , 李政穎 LEE, CHENG YIN , 戴惟璋 TAI, WEI CHANG , 朱吉植 CHU, CHI CHIH
- 申请人： 日月光半導體製造股份有限公司 ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- 申请人地址： 高雄市楠梓加工出口區經三路26號
- 专利权人： 日月光半導體製造股份有限公司 ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- 当前专利权人： 日月光半導體製造股份有限公司 ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- 当前专利权人地址： 高雄市楠梓加工出口區經三路26號
- 代理人： 詹銘文; 蕭錫清
- 主分类号： H01L
- IPC分类号： H01L
A method of fabricating a chip package including following steps is provided. A matrix package substrate is provided, and the bearing face of which has a molding region having multiple chip bearing region. Multiple first conductive elements, electrically connected to the matrix package substrate, are arranged outside the chip bearing region and along the edge of the same. Multiple chips are arranged inside the chip bearing regions, and electrically connected to the matrix package substrate. A molding compound is disposed on the molding region through a molding process for covering the chips and the first conductive elements and exposing part of each first conductive element away from the matrix package substrate. Multiple chip packages are obtained by sawing the molding compound and the matrix package substrate.