基本信息:
- 专利标题： 퓨즈 어드레스 회로
- 专利标题（英）：Circuit of fuse address
- 申请号：KR1020150170933 申请日：2015-12-02
- 公开(公告)号：KR102471411B1 公开(公告)日：2022-11-29
- 主分类号： G11C29/00
- IPC分类号： G11C29/00 ; G11C29/02 ; G11C16/04 ; G11C16/08 ; G11C8/06
摘要：
본발명에따른퓨즈어드레스회로는복수의단위퓨즈들(Fuses), 인접한단위퓨즈들사이에배치되는논리연산자, 및제1 방향으로연장되어단위퓨즈각각과논리연산자를연결하는복수의제1 연결배선들을각각포함하는세 개이상의입력회로들, 및복수개의입력회로들의사이에배치되며퓨즈출력신호를제공하는출력연산자를포함한다. 복수개의입력회로들에구비되는제1 연결배선들은상기제1 방향과실질적으로수직인제2 방향으로동일한높이에형성된다.
摘要（英）：
The present invention relates to a fuse address circuit minimizing a layout area required therefor. The fuse address circuit according to the present invention comprises: at least three input circuits each including a plurality of unit fuses, a logical operator disposed between adjacent unit fuses, and a plurality of first connection wirings extended in a first direction to connect each of the unit fuses and the logical operator; and an output operator disposed between the input circuits and providing a fuse output signal. The first connection wirings provided in the plurality of input circuits are formed at the same height in a second direction substantially perpendicular to the first direction.COPYRIGHT KIPO 2017
公开/授权文献:
- KR1020170064902A 퓨즈 어드레스 회로 公开/授权日：2017-06-12