基本信息:
- 专利标题： 공유 디코더 회로 및 방법
- 专利标题（英）：KR20210028043A - Shared decoder circuit and method
- 申请号：KR20190157759 申请日：2019-11-29
- 公开(公告)号：KR20210028043A 公开(公告)日：2021-03-11
- 优先权： CN201910808044 2019-08-29
- 主分类号： G11C8/10
- IPC分类号： G11C8/10 ; G11C7/22 ; G11C8/06 ; G11C8/08
摘要：
회로는선택회로를포함하고, 선택회로는제 1 입력부에서제 1 어드레스를그리고제 2 입력부에서제 2 어드레스를수신하고, 선택신호가제 1 논리상태를가질때 제 1 어드레스를출력부에전달하고, 선택신호가제 1 논리상태와상이한제 2 논리상태를가질때 제 2 어드레스를출력부에전달하도록구성된다. 상기회로는또한전달된제 1 어드레스또는제 2 어드레스를디코딩하도록구성된디코더를포함한다.
摘要（英）：
The circuit includes a selection circuit, the selection circuit receiving a first address at a first input and a second address at a second input, passing the first address to the output when the selection signal has a first logic state, and , When the selection signal has a second logic state different from the first logic state, it is configured to pass the second address to the output. The circuit also includes a decoder configured to decode the transferred first address or second address.