基本信息:
- 专利标题： 비트 인터리브 방법, 비트 인터리버, 신호 처리방법 및 신호 처리장치
- 专利标题（英）：BIT INTERLEAVE METHOD BIT INTERLEAVER SIGNAL PROCESSING METHOD AND SIGNAL PROCESSING DEVICE
- 申请号：KR1020207036912 申请日：2012-05-18
- 公开(公告)号：KR1020200145856A 公开(公告)日：2020-12-30
- 发明人： 페트로프미하일
- 申请人： 파나소닉 주식회사
- 申请人地址： ****, Oaza Kadoma, Kadoma-shi, Osaka, Japan
- 专利权人： 파나소닉 주식회사
- 当前专利权人： 파나소닉 주식회사
- 当前专利权人地址： ****, Oaza Kadoma, Kadoma-shi, Osaka, Japan
- 代理人： 홍승규
- 优先权： EP110041241 2011-05-18
- 国际申请： PCT/JP2012/003263 2012-05-18
- 国际公布： WO2012157283 2012-11-22
- 主分类号： H03M13/27
- IPC分类号： H03M13/27 ; H03M13/19
Bit interleaving method for interleaving a QC-LDPC codeword made up of N cyclic blocks each consisting of Q cyclic block bits and the constellation word being made up of M bits with N being not a multiple of M. The bit interleaving comprises a cyclic block permutation step, a bit permutation step and a dividing step, where the N-N' cyclic blocks, with N' = N - remainder (N/M), are excluded from the bit permutation process. After the cyclic block permutation process, the N' cyclic blocks are divided so that the Q bits in each of the N' cyclic block are each allocated to a bit of an identical bit index in Q constellation words and said Q constellation words are each made up of one bit from each of M different cyclic blocks, said M different cyclic blocks being common to said Q constellation words.
公开/授权文献:
- KR102233156B1 비트 인터리브 방법, 비트 인터리버, 신호 처리방법 및 신호 처리장치 公开/授权日：2021-03-26
信息查询:
EspacenetIPC结构图谱:
| H | 电学 |
| --H03 | 基本电子电路 |
| ----H03M | 一般编码、译码或代码转换 |
| ------H03M13/00 | 用于检错或纠错的编码、译码或代码转换；编码理论基本假设；编码约束；误差概率估计方法；信道模型；代码的模拟或测试 |
| --------H03M13/27 | .应用交错技术的 |