基本信息:
- 专利标题： 평탄화에 의한 감소된 땜납 패드 토폴로지 차이를 포함하는 전자 구조를 제조하는 방법, 및 대응하는 전자 구조
- 专利标题（英）：Method of manufacturing an electronic structure comprising reducing solder pad topology differences by planarization and corresponding electronic structure
- 专利标题（中）：通过平面化和相应的电子结构制造包含减少焊料平台拓扑差异的电子结构的方法
- 申请号：KR1020167001992 申请日：2014-06-05
- 公开(公告)号：KR1020160022917A 公开(公告)日：2016-03-02
- 发明人： 레이,지푸 , 시아피노,스테파노 , 니켈,알렉산더에이치. , 엔지,무이구안 , 아크람,살만
- 申请人： 코닌클리케 필립스 엔.브이.
- 申请人地址： High Tech Campus *, **** AE Eindhoven, The Netherlands
- 专利权人： 코닌클리케 필립스 엔.브이.
- 当前专利权人： 코닌클리케 필립스 엔.브이.
- 当前专利权人地址： High Tech Campus *, **** AE Eindhoven, The Netherlands
- 代理人： 양영준; 백만기
- 优先权： US61/838,457 2013-06-24
- 国际申请： PCT/IB2014/061968 2014-06-05
- 国际公布： WO2014207590 2014-12-31
- 主分类号： H01L23/00
- IPC分类号： H01L23/00 ; H01L21/48 ; H01L23/498
The top surface of the solder bumps on the chip 40 to ensure a more reliable bond between the chip 40 and substrate 62 are provided a technology for enabling the same plane. The chip 40 is provided with the solder pad, which may have different heights (42, 44). A dielectric layer (50) is formed between the soldering pads (42, 44). This relatively thick metal layer 52 is plated over the solder pads (42, 44). Metal layer 52 is planarized in order to be on the solder pads (42, 44) above the metal layer 52, dielectric layer 50, the upper surface is in the same plane of section. It is substantially of a layer of a thin uniform solder 58, with the top surface of the solder bumps are, substantially parallel to the upper surface of the chip 40, or to achieve an angle to the upper surface of the chip 40, a substantially to the same plane, it is deposited over the planarized metal layer portion (52). Chip 40 is disposed on the substrate 62 with the corresponding metal pad (64) Then, the solder 58 is reflowed, or ultrasonic bonding to the substrate pads 64.
公开/授权文献:
信息查询:
EspacenetIPC结构图谱:
| H | 电学 |
| --H01 | 基本电气元件 |
| ----H01L | 半导体器件；其他类目未包含的电固体器件 |
| ------H01L23/00 | 半导体或其他固态器件的零部件 |