基本信息:
- 专利标题： 프로세서 모드들을 스위칭하기 위해 호출된 함수의 어드레스의 최하위 비트들의 이용
- 专利标题（英）：Using the least significant bits of a called function's address to switch processor modes
- 专利标题（中）：使用呼叫功能地址的最小重要位置切换处理器模式
- 申请号：KR1020147025017 申请日：2013-02-07
- 公开(公告)号：KR1020140123576A 公开(公告)日：2014-10-22
- 发明人： 타보니,찰스조셉 , 플론드케,에리치제임스 , 코드레스쿠,루시안 , 벤쿠마한티,수레쉬케이. , 메네제스,에반드로카를로스
- 申请人： 퀄컴 인코포레이티드
- 申请人地址： **** Morehouse Drive, San Diego, CA *****-****, U.S.A.
- 专利权人： 퀄컴 인코포레이티드
- 当前专利权人： 퀄컴 인코포레이티드
- 当前专利权人地址： **** Morehouse Drive, San Diego, CA *****-****, U.S.A.
- 代理人： 특허법인 남앤드남
- 优先权： US13/655,499 2012-10-19; US61/595,773 2012-02-07
- 国际申请： PCT/US2013/025187 2013-02-07
- 国际公布： WO2013119842 2013-08-15
- 主分类号： G06F9/30
- IPC分类号： G06F9/30 ; G06F9/32
Track the execution mode from the processing system and is provided with systems and methods for switching between them. The processing system is configured to execute instructions in at least two instruction execution modes including the first and second running mode is selected from the classical / aligned mode, and the compression / non-sort mode. Target address of the selected command and the call and return have been misaligned force in the compressed mode, this at least one bit as the least significant bits of the target address in the compressed mode (the alignment bits) are the corresponding alignment of the classic mode, it is different from the bit. When that selected instruction is encountered during the execution of the first mode, the judgment as to the switching of operation to the second mode is based on analysis of the aligned bits of the target address of the selected instruction.
公开/授权文献:
- KR101847889B1 프로세서 모드들을 스위칭하기 위해 호출된 함수의 어드레스의 최하위 비트들의 이용 公开/授权日：2018-04-11
信息查询:
EspacenetIPC结构图谱:
| G | 物理 |
| --G06 | 计算；推算；计数 |
| ----G06F | 电数字数据处理 |
| ------G06F9/00 | 电数字数据处理的控制单元 |
| --------G06F9/06 | .应用存入的程序的，即应用处理设备的内部存储来接收程序并保持程序的 |
| ----------G06F9/30 | ..执行机器指令的装置，例如指令译码 |