基本信息:
- 专利标题： 실리콘 관통 비아를 사용한 집적 회로 구조물
- 专利标题（英）：Integrated circuit design using through silicon vias
- 专利标题（中）：集成电路采用硅六角形设计
- 申请号：KR1020137033346 申请日：2012-01-16
- 公开(公告)号：KR1020140039227A 公开(公告)日：2014-04-01
- 发明人： 라흐만아리푸르
- 申请人： 자일링크스 인코포레이티드
- 申请人地址： 미합중국 ***** 캘리포니아 산 호세 로직 드라이브 ****
- 专利权人： 자일링크스 인코포레이티드
- 当前专利权人： 자일링크스 인코포레이티드
- 当前专利权人地址： 미합중국 ***** 캘리포니아 산 호세 로직 드라이브 ****
- 代理人： 김태홍
- 优先权： US13/170,020 2011-06-27
- 国际申请： PCT/US2012/021416 2012-01-16
- 国际公布： WO2013002844 2013-01-03
- 主分类号： H01L23/48
- IPC分类号： H01L23/48 ; H01L25/07 ; H01L23/522
In integrated circuit (IC) structure, and with regard to the physical layout of the circuit is that techniques for placing the silicon through vias (TSV). IC structure is a plurality of first circuit elements (D1, G1, and S; 702, 706, 710, and 714; or 702, 706, 704, and 708); A plurality of second circuit elements (D2, G2, and S; 704, 708, 712, and 716; or 710, 714, 712, and 716); A plurality of the TSV 1 (410 and 510; 605 to 620; or 720 to 734); And a plurality of the 2 TSV may include a (415 and 505; or 736 to 750; 625 to 640). The constitutes a first and a second circuit element with a first configuration and a second circuit block with the TSV. Circuit block diagram is symmetrical about at least one axis of symmetry. Claim 1 wherein at least one of the TSV is a dummy TSV (dummy TSV), this will be if there is no dummy TSV is a circuit block configured to be symmetrical.
公开/授权文献:
- KR101770877B1 실리콘 관통 비아를 사용한 집적 회로 구조물 公开/授权日：2017-08-23
信息查询:
EspacenetIPC结构图谱:
| H | 电学 |
| --H01 | 基本电气元件 |
| ----H01L | 半导体器件；其他类目未包含的电固体器件 |
| ------H01L23/00 | 半导体或其他固态器件的零部件 |
| --------H01L23/48 | .用于向或自处于工作中的固态物体通电的装置，例如引线、接线端装置 |