基本信息:
- 专利标题： 비휘발성 메모리들에서 포인터 기반 컬럼 선택 기술들
- 专利标题（英）：Pointer based column selection techniques in non-volatile memories
- 专利标题（中）：非易失性存储器中基于指针的色谱柱选择技术
- 申请号：KR1020117030720 申请日：2010-06-15
- 公开(公告)号：KR1020120108917A 公开(公告)日：2012-10-05
- 发明人： 칩봉고드제,하드웰 , 사카이,마나부 , 카메이,테루히코
- 申请人： 샌디스크 테크놀로지스 엘엘씨
- 申请人地址： Two Legacy Town Center, **** Dallas Parkway, Plano, Texas *****, U.S.A.
- 专利权人： 샌디스크 테크놀로지스 엘엘씨
- 当前专利权人： 샌디스크 테크놀로지스 엘엘씨
- 当前专利权人地址： Two Legacy Town Center, **** Dallas Parkway, Plano, Texas *****, U.S.A.
- 代理人： 박경재
- 优先权： US12/490,655 2009-06-24
- 国际申请： PCT/US2010/038616 2010-06-15
- 国际公布： WO2011005427 2011-01-13
- 主分类号： G11C16/06
- IPC分类号： G11C16/06 ; G11C16/08 ; G11C7/10 ; G11C8/18
The selection of circuits for the columns of the array of memory cells are used to maintain the read data or write data of the memory cells. In embodiments of the first set, the shift register chain having a stage for the columns of the array is provided with a column that is arranged in a loop. For example, alternating columns or column groups can be accessed when the pointer is moved in a first direction across the array, and the other half of the columns are accessed when the pointer moves back in the other direction. Examples of the other set of columns one by one, each set of columns that is clocked at half-speed, divided into two groups and use the pointer interleaved in pairs. To control the access of the two sets, each of which is connected to intermediate data bus corresponding. The intermediate data bus are attached to the combined data bus is clocked at full speed after that.