基本信息:
- 专利标题： 반도체 메모리 및 프로그램
- 专利标题（英）：Semiconductor memory and program
- 专利标题（中）：半导体存储器和程序
- 申请号：KR1020107016180 申请日：2009-01-07
- 公开(公告)号：KR1020100101148A 公开(公告)日：2010-09-16
- 发明人： 요시모토마사히코 , 카와구치히로시 , 후지와라히데히로 , 오쿠무라슌스케
- 申请人： 코에키자이단호우진 신산교소우조우 겐큐키코
- 申请人地址： *-* Minatojima-Nakamachi, Chuo-ku, Kobe-shi, Hyogo Japan
- 专利权人： 코에키자이단호우진 신산교소우조우 겐큐키코
- 当前专利权人： 코에키자이단호우진 신산교소우조우 겐큐키코
- 当前专利权人地址： *-* Minatojima-Nakamachi, Chuo-ku, Kobe-shi, Hyogo Japan
- 代理人： 특허법인원전
- 优先权： JPJP-P-2008-000357 2008-01-07
- 国际申请： PCT/JP2009/050086 2009-01-07
- 国际公布： WO2009088020 2009-07-16
- 主分类号： G11C11/41
- IPC分类号： G11C11/41 ; G11C11/412
According to the application or the memory situation, it is possible to dynamically change the bit reliability of the memory cell, ensure the stability of the operation provides a possible realize lower power consumption and higher reliability memory. 1 bit is one in which the memory cell configuration mode (1-bit / 1-cell mode), and one bit is n and dynamically switches the mode (1-bit / n-cell mode), that is configured to connect the (n is 2 or more) memory cell . By conversion to the 1-bit / n-cell mode, the cell 1 is performed to increase the current of the read / increase stability of the recording and reading operations of the bead (speeding up of the read operation), also performs a self-restoration of the bit error. In particular, the CMOS transistor of the pair between the data holding nodes of the adjacent n memory cells, to the CMOS-up transistor is added one more control lines for controlling to conduction which controls the word line (WL), the further operation to improve the stability.
公开/授权文献:
- KR101569540B1 반도체 메모리 및 프로그램 公开/授权日：2015-11-16