基本信息:
- 专利标题： 메모리 회로를 포함하는 집적 회로 및 그 형성 방법
- 专利标题（英）：Layout techniques for read-only memory and the like
- 专利标题（中）：只读存储器和类似的布局技术
- 申请号：KR1020070019562 申请日：2007-02-27
- 公开(公告)号：KR1020070089088A 公开(公告)日：2007-08-30
- 发明人： 두덱크데니스이 , 에반스도널드에이 , 팜하이큐 , 워너웨인이 , 워즈니악로널드제이
- 申请人： 에이저 시스템즈 엘엘시
- 申请人地址： **** American Parkway NE, Allentown, Pennsylvania *****, U.S.A.
- 专利权人： 에이저 시스템즈 엘엘시
- 当前专利权人： 에이저 시스템즈 엘엘시
- 当前专利权人地址： **** American Parkway NE, Allentown, Pennsylvania *****, U.S.A.
- 代理人： 제일특허법인; 김원준
- 优先权： US11/363,010 2006-02-27
- 主分类号： G11C17/00
- IPC分类号： G11C17/00 ; G11C7/18 ; G11C8/14
摘要：
An integrated circuit including a memory circuit and a forming method thereof are provided to enable a switching device connected between an adjacent word line and a selected bit line of an adjacent bit line structure to have selective conductivity according to the enabling by the adjacent word line. An integrated circuit includes a memory circuit(100). Each of a plurality of bit lines(102) includes at least three bit lines. A plurality of word lines(110) crosses with the bit line structure at plural sites(112). A plurality of switching devices is located at the selected sites individually. A plurality of Vss planes is connected to the switching device. The switching device and the Vss plane are formed at a first level, and the Vss plane is formed as complementary interlocking regions forming a functional part of the switching device. The switching device is connected between an adjacent word line and a selected bit line of an adjacent bit line structure and has selective conductivity between the word and bit lines according to the enabling due to the adjacent word line.
摘要（中）：
提供一种包括存储器电路及其形成方法的集成电路，用于使相邻字线和相邻位线结构的选定位线之间连接的开关器件能够根据相邻字线的使能而具有选择性导电性。 集成电路包括存储器电路（100）。 多个位线（102）中的每一个包括至少三个位线。 多个字线（110）在多个位置（112）处与位线结构交叉。 多个切换装置分别位于所选择的部位。 多个Vss平面连接到开关装置。 开关装置和Vss平面形成在第一级，并且Vss平面形成为形成开关装置的功能部分的互补互锁区域。 开关装置连接在相邻字线和相邻位线结构的选定位线之间，并且由于相邻字线由于使能而在字和位线之间具有选择性的电导率。
公开/授权文献:
- KR101333436B1 메모리 회로를 포함하는 집적 회로 및 그 형성 방법 公开/授权日：2013-11-26