基本信息:
- 专利标题: 반도체 장치 및 메모리 시스템
- 专利标题(英):Semiconductor device and memory system
- 专利标题(中):制造半导体器件的半导体器件和存储器系统,并提高电气特性
- 申请号:KR1020040072801 申请日:2004-09-11
- 公开(公告)号:KR1020040087985A 公开(公告)日:2004-10-15
- 发明人: 사쿠마가즈키 , 카와무라마사야스 , 타카하시야스시 , 마스다마사치카 , 와다타마키 , 스기야마미치아키 , 니시자와히로타카 , 스가노토시오
- 申请人: 가부시키가이샤 히타치세이사쿠쇼 , 가부시키가이샤 히타치초에루. 에스. 아이. 시스테무즈
- 申请人地址: *-*, Marunouchi *-chome, Chiyoda-ku, Tokyo, Japan
- 专利权人: 가부시키가이샤 히타치세이사쿠쇼,가부시키가이샤 히타치초에루. 에스. 아이. 시스테무즈
- 当前专利权人: 가부시키가이샤 히타치세이사쿠쇼,가부시키가이샤 히타치초에루. 에스. 아이. 시스테무즈
- 当前专利权人地址: *-*, Marunouchi *-chome, Chiyoda-ku, Tokyo, Japan
- 代理人: 특허법인원전
- 优先权: JPJP-P-1998-00335351 1998-11-26
- 主分类号: H01L23/12
- IPC分类号: H01L23/12
摘要:
PURPOSE: A semiconductor device is provided to make a semiconductor device thin by making a resin sealing member thin, and to improve an electrical characteristic by greatly reducing the floating capacitance of a lead. CONSTITUTION: A resin sealing member(12) is prepared. The first semiconductor chip has the first and second outer terminals on a circuit formation surface. The second semiconductor chip has the third and fourth outer terminals on a circuit formation surface. The first, second and third leads extend to the inside and outside of the resin sealing member. The first lead is ramified into two in at least the resin sealing member. One of the ramified first lead is fixed to the circuit formation surface of the first semiconductor chip. The other of the ramified first lead is fixed to the circuit formation surface of the second semiconductor chip. The second lead is fixed to the circuit formation surface of the first semiconductor chip, connected to the second outer terminal. The third lead is fixed to the circuit formation surface of the second semiconductor chip, connected to the fourth outer terminal. The first and second semiconductor chips are operated by a clock signal supplied to the first lead while the back surfaces of the chips face each other. The first and second chip control signals are input from the outside of the resin sealing member to the second and third leads to make the first and second semiconductor chips be in a low power consumption mode, respectively.
摘要(中):
目的:提供半导体器件,通过使树脂密封构件变薄而使半导体器件变薄,并且通过大大降低引线的浮置电容来改善电特性。 构成:制备树脂密封件(12)。 第一半导体芯片在电路形成表面上具有第一和第二外部端子。 第二半导体芯片在电路形成表面上具有第三和第四外部端子。 第一,第二和第三引线延伸到树脂密封构件的内部和外部。 至少树脂密封部件中的第一引线分成两部分。 分支的第一引线中的一个固定到第一半导体芯片的电路形成表面。 分支的第一引线中的另一个固定到第二半导体芯片的电路形成表面。 第二引线固定在与第二外部端子连接的第一半导体芯片的电路形成表面上。 第三引线固定在与第四外部端子连接的第二半导体芯片的电路形成表面上。 第一和第二半导体芯片由提供给第一引线的时钟信号操作,而芯片的背面彼此面对。 第一和第二芯片控制信号从树脂密封构件的外部输入到第二和第三引线,以使第一和第二半导体芯片分别处于低功耗模式。
信息查询:
EspacenetIPC结构图谱:
H | 电学 |
--H01 | 基本电气元件 |
----H01L | 半导体器件;其他类目未包含的电固体器件 |
------H01L23/00 | 半导体或其他固态器件的零部件 |
--------H01L23/12 | .安装架,例如不可拆卸的绝缘衬底 |