基本信息:
- 专利标题: 반도체 장치의 캐패시터 제조방법
- 专利标题(英):Method for fabricating capacitor in semiconductor device
- 专利标题(中):用于制造半导体器件电容器的方法
- 申请号:KR1020020086252 申请日:2002-12-30
- 公开(公告)号:KR1020040059750A 公开(公告)日:2004-07-06
- 发明人: 최은석 , 염승진
- 申请人: 에스케이하이닉스 주식회사
- 申请人地址: 경기도 이천시 부발읍 경충대로 ****
- 专利权人: 에스케이하이닉스 주식회사
- 当前专利权人: 에스케이하이닉스 주식회사
- 当前专利权人地址: 경기도 이천시 부발읍 경충대로 ****
- 代理人: 특허법인신성
- 主分类号: H01L27/108
- IPC分类号: H01L27/108
摘要:
PURPOSE: A method for fabricating a capacitor of a semiconductor device is provided to save money by eliminating the necessity of a CMP(chemical mechanical polishing) process when a lower electrode is formed and a planarization process is performed, and to more reliably fabricate a capacitor by preventing the surface of the lower electrode from being damaged by a CMP process. CONSTITUTION: A metal layer for a lower electrode is formed on a substrate(20). A buffer layer for an etch-back process is formed on the metal layer for the lower electrode, made of a material having different etch selectivity from that of the metal layer. The metal layer for the lower electrode and the buffer layer are selectively removed to form the lower electrode and a buffer layer pattern. An interlayer dielectric is formed to cover the lower electrode and the buffer layer pattern. An etch-back process is performed to remove the interlayer dielectric to the lower part of the buffer layer. The buffer layer is eliminated. A dielectric thin film is formed on the lower electrode. An upper electrode is formed on the dielectric thin film.
摘要(中):
目的:提供一种制造半导体器件的电容器的方法,以便在形成下电极并执行平面化处理时,通过消除CMP(化学机械抛光)处理的必要性来节省成本,并且更可靠地制造电容器 通过防止下部电极的表面被CMP处理损坏。 构成:在基板(20)上形成用于下电极的金属层。 在用于下电极的金属层上形成用于回蚀工艺的缓冲层,由与金属层的蚀刻选择性不同的材料制成。 选择性地去除用于下电极和缓冲层的金属层以形成下电极和缓冲层图案。 形成层间电介质以覆盖下电极和缓冲层图案。 执行回蚀处理以将层间电介质去除到缓冲层的下部。 缓冲层被消除。 在下电极上形成电介质薄膜。 在电介质薄膜上形成上电极。
信息查询:
EspacenetIPC结构图谱:
H | 电学 |
--H01 | 基本电气元件 |
----H01L | 半导体器件;其他类目未包含的电固体器件 |
------H01L27/00 | 由在一个共用衬底内或其上形成的多个半导体或其他固态组件组成的器件 |
--------H01L27/02 | .包括有专门适用于整流、振荡、放大或切换的半导体组件并且至少有一个电位跃变势垒或者表面势垒的;包括至少有一个跃变势垒或者表面势垒的无源集成电路单元的 |
----------H01L27/04 | ..其衬底为半导体的 |
------------H01L27/06 | ...在非重复结构中包括有多个单个组件的 |
--------------H01L27/105 | ....包含场效应组件的 |
----------------H01L27/108 | .....动态随机存取存储结构的 |