基本信息:
- 专利标题: 금속 라우팅 저항이 감소된 디스플레이 회로
- 专利标题(英):KR101837343B1 - Display circuitry with reduced metal routing resistance
- 申请号:KR1020170047940 申请日:2017-04-13
- 公开(公告)号:KR101837343B1 公开(公告)日:2018-03-09
- 发明人: 첸,유쳉 , 창,시흐-창 , 오사와,히로시 , 창,팅-쿠오
- 申请人: 애플 인크.
- 申请人地址: * Infinite Loop, Cupertino, California *****, U.S.A.
- 专利权人: 애플 인크.
- 当前专利权人: 애플 인크.
- 当前专利权人地址: * Infinite Loop, Cupertino, California *****, U.S.A.
- 代理人: 양영준; 백만기
- 优先权: US14/150,458 2014-01-08
- 主分类号: G02F1/136
- IPC分类号: G02F1/136 ; G02F1/1368 ; G02F1/1362 ; H01L29/786 ; H01L27/12
The display may be provided with a color filter layer and a thin film transistor layer. Layer of a liquid material can be positioned between the color filter and thin film transistor (TFT) layer. TFT layer may comprise a thin film transistor formed on the glass substrate. It can be a passivation layer formed on the thin film transistor layer. On the passivation layer is an oxide liner can be formed. There is a first low-k dielectric layer on the oxide liner can be formed. The first may be the second low-k dielectric layer formed over the low-k dielectric layer. The second may be a common electrode voltage and the associated storage capacitances formed on the low-k dielectric layer. May be a thin film transistor gate structure are formed on the passivation layer. On the oxide liner, the first may be routed conductive structure are formed on the low dielectric constant on the dielectric layer, and a second low-k dielectric layer. The use of the routing structure on the oxide liner, reducing the overall resistance and routing, enables the interlaced metal routing, which can help reduce the inactive border area outside the active display area.
公开/授权文献:
- KR1020170047198A 금속 라우팅 저항이 감소된 디스플레이 회로 公开/授权日:2017-05-04