The present invention relates to a liquid crystal display device, each of the source drive IC of the liquid crystal display device is PLL to reduce jitter of the external clock signal, receiving the external clock signal; DLL claim 1 which generates an internal clock based on the data that is synchronized with the delayed clock signal output from the PLL; DLL of claim 2 for generating an internal clock signal period equal parts (× 3 bits of the data is N) N in the inside of the reference clock to delay the internal clock, the reference; Sampler for sampling the data based on the internal clock signal outputted from the DLL of claim 2; DLL to claim 3 for receiving an external clock signal prior to input to the PLL delay the external clock signal for generating an internal clock signal N equally divided uniformly in one period of the external clock signal; And an ESD detector for detecting a noise period of the external clock signal based on the internal clock signal outputted from the DLL of claim 3.