Clock signal generating circuit delays the read command signal generates an internal read command signal and the external clock signal generation circuit for generating a frequency division of the first clock signal from the signal phase and the control clock phases of the signals of the first clock signal compare, and determining unit for outputting a clock signal having the same phase or the opposite phase as the phase of the first clock signal and the control signal as a result of the comparison, by delaying the clock signal a and generate a first latency control clock signal, to the second clock signal frequency division from the external clock signal delayed by a plurality of delay circuit and generating the control clock signal, the second latency control clock for generating a plurality of second latency control clock signal from the clock signal and the signal generating unit, and to the first latency control clock signal includes the use of a plurality of second latency control clock signal a latency occurs for outputting the control latency of the internal read command signal and latency controlled latency signal, It said plurality of delay circuits are enabled and disabled in response to the control signal. DLL circuit, the PLL circuit, the clock domain, CAS latency