基本信息:
- 专利标题： 프로그래머블 로직 디바이스
- 专利标题（英）：Programmable Logic Device
- 专利标题（中）：可编程逻辑器件
- 申请号：KR1020147009330 申请日：2012-05-08
- 公开(公告)号：KR101466885B1 公开(公告)日：2014-12-03
- 发明人： 요네다세이이치 , 니시지마타츠지
- 申请人： 가부시키가이샤 한도오따이 에네루기 켄큐쇼
- 申请人地址： 일본국 가나가와켄 아쓰기시 하세 ***
- 专利权人： 가부시키가이샤 한도오따이 에네루기 켄큐쇼
- 当前专利权人： 가부시키가이샤 한도오따이 에네루기 켄큐쇼
- 当前专利权人地址： 일본국 가나가와켄 아쓰기시 하세 ***
- 代理人： 황의만
- 优先权： JPJP-P-2011-112045 2011-05-19
- 国际申请： PCT/JP2012/062246 2012-05-08
- 国际公布： WO2012157593 2012-11-22
- 主分类号： H03K19/177
- IPC分类号： H03K19/177
It is an object of the present invention to provide a programmable logic device having a logical block connected to each other by a programmable switch, in this case, a programmable switch is characterized in the oxide semiconductor transistor integrated therein. Oxide very low off current of the semiconductor transistor and provides a function as a non-volatile memory due to its ability to hold the potential of the gate electrode of the transistor connected to the oxide semiconductor transistor. Ability of the oxide semiconductor transistor which functions as a non-volatile memory allows the container illustration figure data for controlling the connection of a logical block is held even when the supply of power supply potential barrier. Accordingly, the process of writing the data starts when containers figure illustration of the device again may be omitted, which contributes to reduction in power consumption of the device.
公开/授权文献:
- KR1020140049096A 프로그래머블 로직 디바이스 公开/授权日：2014-04-24
信息查询:
EspacenetIPC结构图谱:
| H | 电学 |
| --H03 | 基本电子电路 |
| ----H03K | 脉冲技术 |
| ------H03K19/00 | 逻辑电路，即，至少有两个输入作用于一个输出的；倒向电路 |
| --------H03K19/01 | .提高开关速度的改进 |
| ----------H03K19/173 | ..应用基本逻辑电路作组件的 |
| ------------H03K19/177 | ...矩阵式排列的 |