基本信息:
- 专利标题： 낮은 클록 에너지, 완전 정적 래치 회로
- 专利标题（英）：Low-clock-energy, fully-static latch circuit
- 专利标题（中）：低能量，全静态电压电路
- 申请号：KR1020120015340 申请日：2012-02-15
- 公开(公告)号：KR101317112B1 公开(公告)日：2013-10-11
- 发明人： 델리,윌리암제이.
- 申请人： 엔비디아 코포레이션
- 申请人地址： **** SAN TOMAS EXPRESSWAY, SANTA CLARA, CALIFORNIA ***** U.S.A.
- 专利权人： 엔비디아 코포레이션
- 当前专利权人： 엔비디아 코포레이션
- 当前专利权人地址： **** SAN TOMAS EXPRESSWAY, SANTA CLARA, CALIFORNIA ***** U.S.A.
- 代理人： 양영준; 백만기
- 优先权： US13/028,023 2011-02-15
- 主分类号： H03K3/037
- IPC分类号： H03K3/037
One embodiment of the invention using a completely static low energy clock latch circuit will be described a technique to capture and hold the level of the input signal. Clock is the first clock enable pull-up transistor is coupled only-up or pull-down transistor and a second clock enable pull-down or pull. Level of the input signal is rising or falling clock captured and stored by the storage sub-circuit in one of the edges and generating an output signal until the clock transitions. Level of the input signal is propagated to the output signal when not enable the storage of the sub-circuit. Storage sub-circuit is enabled and disabled by the active first clock transistor, the radio sub-circuit is activated and deactivated by activating the second clock transistor.
公开/授权文献:
- KR1020120093789A 낮은 클록 에너지, 완전 정적 래치 회로 公开/授权日：2012-08-23