基本信息:
- 专利标题： 프렉셔널-Ｎ 위상 록킹 루프에서의 델타-시그마 변조기 클록 디더링
- 专利标题（英）：Delta-sigma modulator clock dithering in a fractional-n phase-locked loop
- 专利标题（中）：DELTA-SIGMA调制器时钟在一个分段N相锁定环路
- 申请号：KR1020107021258 申请日：2009-02-26
- 公开(公告)号：KR101228396B1 公开(公告)日：2013-01-31
- 发明人： 쉬양 , 장강 , 구뎀프라사드에스
- 申请人： 퀄컴 인코포레이티드
- 申请人地址： **** Morehouse Drive, San Diego, CA *****-****, USA
- 专利权人： 퀄컴 인코포레이티드
- 当前专利权人： 퀄컴 인코포레이티드
- 当前专利权人地址： **** Morehouse Drive, San Diego, CA *****-****, USA
- 代理人： 특허법인코리아나
- 优先权： US12/037,503 2008-02-26
- 国际申请： PCT/US2009/035349 2009-02-26
- 国际公布： WO2009108815 2009-09-03
- 主分类号： H03L7/197
- IPC分类号： H03L7/197 ; H03M7/00
Fractional -N delta of the phase locked loop is a clock signal supplied to the sigma modulator dithering. In one example, PLL comprises a novel programmable clock dithering circuit. A selected one of several ways how to dithering the phase of the clock signal the programmable clock dithering circuit is controllable via a serial bus. If the clock signal is dithered in one way (a pseudo-random phase dithering), delta - being a power of the digital noise generated by the sigma modulator spreads through the band, reduces the degree to which the noise interferes with the other circuits. If the clock signal is dithered in two ways (the rotational phase dithering), the power of digital noise is the frequency shift reduces the extent to which the noise interferes with the other circuits. Program clock dithering circuit can may be controlled in different ways. For example, the dither may be disabled enabling program.
公开/授权文献:
- KR1020100115381A 프렉셔널-Ｎ 위상 록킹 루프에서의 델타-시그마 변조기 클록 디더링 公开/授权日：2010-10-27
信息查询:
EspacenetIPC结构图谱:
| H | 电学 |
| --H03 | 基本电子电路 |
| ----H03L | 电子振荡器或脉冲发生器的自动控制、起振、同步或稳定 |
| ------H03L7/00 | 频率或相位的自动控制；同步 |
| --------H03L7/02 | .应用由无源频率确定元件组成的鉴频器的 |
| ----------H03L7/08 | ..锁相环的零部件 |
| ------------H03L7/18 | ...在该环中应用分频器或计数器的 |
| --------------H03L7/197 | ....将时间差用于锁定环路，并且计数器在随时间变化的数字之间进行计数或分频器以随时间变化的因数进行分频的，例如用于获得分级分频的 |