基本信息:
- 专利标题： 출력 데이터의 스큐를 감소시킬 수 있는 출력버퍼 회로
- 专利标题（英）：Output buffer circuit capable of reducing skew of output data
- 专利标题（中）：输出缓冲电路，能够减少输出数据的偏移
- 申请号：KR1020020067745 申请日：2002-11-04
- 公开(公告)号：KR100498453B1 公开(公告)日：2005-07-01
- 发明人： 김정열
- 申请人： 삼성전자주식회사
- 申请人地址： ***, Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, Republic of Korea
- 专利权人： 삼성전자주식회사
- 当前专利权人： 삼성전자주식회사
- 当前专利权人地址： ***, Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, Republic of Korea
- 代理人： 리앤목특허법인
- 主分类号： G11C11/40
- IPC分类号： G11C11/40
Even if the PVT variation is an output buffer circuit for reducing the skew of the output data is disclosed. It said output buffer circuit comprises: a pull-up transistor and the pull-down transistor, the PMOS of the path from the NAND gates for driving the pull-up transistor, and includes a NOR gate for driving the pull-down transistor, in particular from power supply voltage to the NAND gate output wherein from the output of the PMOS an NMOS transistor count in the path to the ground voltage, equal to the number of transistors, and from the output of the NAND gate of the NOR gate in the path to the NOR gate output terminal from the number of transistors the supply voltage yen of the path from the ground voltage to the same is characterized in that the number of MOS transistors.
公开/授权文献:
- KR1020040039617A 출력 데이터의 스큐를 감소시킬 수 있는 출력버퍼 회로 公开/授权日：2004-05-12
信息查询:
EspacenetIPC结构图谱:
| G11C11/56 | 组优先于G11C11/02至G11C11/54中各组。 |
| --G11C11/19 | .在谐振电路中应用非线性电抗器件的 |
| ----G11C11/26 | ..应用放电管的 |
| ------G11C11/40 | ...应用晶体管的 |