The present invention relates to a PCM data delay circuit for delay time in the output PCM data by reading the PCM after the data was temporarily stored in the memory a certain period of time. The invention in accordance with the operation clock provided for PCM data in the serial form received over the sub-highway (SHW) transmitting and receiving means and the sub-Highway transmitting and receiving means for transmitting and receiving PCM data in predetermined channels of a serial form received from the time switch device is converted to parallel data of a predetermined number of bits to store in memory, or converted by the serial / parallel and parallel / serial converting means for parallel-type converts the PCM data in series stored in the memory, and serial / parallel and parallel / serial converting means and a memory for temporarily storing the PCM data, and delay time setting means for setting a delay time of the data during the initial or operations, the sub-highway transmission means from the set of the delay time setting means according to the clock and sync pulses supplied values ​​and memory by comparing the write address, reset the read address of the memory, or for writing to or reading from the memory Providing a dress and an access control signal, and consists of a comparison and control means for providing an operating clock to the serial / parallel and parallel / serial conversion means is that the number of delay for a certain frame of the PCM data of a predetermined channel.