基本信息:
- 专利标题： Delay circuit
- 专利标题（中）：延时电路
- 申请号：JP16723084 申请日：1984-08-08
- 公开(公告)号：JPS6145621A 公开(公告)日：1986-03-05
- 发明人： ASO MAKOTO
- 申请人： Makoto Aso
- 专利权人： Makoto Aso
- 当前专利权人： Makoto Aso
- 优先权： JP16723084 1984-08-08
- 主分类号： H03H11/26
- IPC分类号： H03H11/26
摘要：
PURPOSE: To obtain a delay circuit excellent in leading and trailing edges by keeping a gate of a FET at a prescribed potential and grounding one end of a channel via a capacitor.
CONSTITUTION: When a switch 8 is closed, charging to a capacitor 3 is started through a resistor 4 and a FET1 and the source potential of the FET1 is increased. When a source potential approaches a gate potential, an electric field is fed to the FET1 and the drain potential of the FET1 rises earlier than the source potential. When the drain potential of the FET1 breaks down a Zener diode 5, a load current is obtained from a collector of a transistor 6.
COPYRIGHT: (C)1986,JPO&Japio
摘要（中）：
CONSTITUTION: When a switch 8 is closed, charging to a capacitor 3 is started through a resistor 4 and a FET1 and the source potential of the FET1 is increased. When a source potential approaches a gate potential, an electric field is fed to the FET1 and the drain potential of the FET1 rises earlier than the source potential. When the drain potential of the FET1 breaks down a Zener diode 5, a load current is obtained from a collector of a transistor 6.
COPYRIGHT: (C)1986,JPO&Japio
目的：通过将FET的栅极保持在规定的电位并通过电容器对通道的一端进行接地，以获得前沿和后沿优异的延迟电路。 构成：当开关8闭合时，通过电阻器4和FET1开始对电容器3的充电，并且FET1的源极电位增加。 当源极电位接近栅极电位时，电场被馈送到FET1，并且FET1的漏极电势比源极电位上升。 当FET1的漏极电位破坏齐纳二极管5时，从晶体管6的集电极获得负载电流。
公开/授权文献:
- JPS6182493U JPS6182493U - 公开/授权日：1986-05-31