PROBLEM TO BE SOLVED: To shorten the time until a processor can read and write data from and to a memory while reducing power consumption.SOLUTION: A memory controller of an embodiment includes a clock switching unit and a control signal switching unit. The clock switching unit is inputted a first clock and a second clock which has a higher frequency than that of the first clock; supplies the first clock to a memory until the second clock becomes stable; and supplies the second clock to the memory after the second clock becomes stable. When the first clock is being supplied to the memory, the control signal switching unit starts supplying a first control signal, which initializes the memory to a state in which data can be read and written by a processor, to the memory; and the second clock is supplied to the memory and after the memory is initialized, the signal switching unit supplies a second control signal according to the read or write of data by the processor, to the memory.