基本信息:
- 专利标题: Manufacturing method and design method for wiring board
- 专利标题(中):接线板的制造方法和设计方法
- 申请号:JP2009231856 申请日:2009-10-05
- 公开(公告)号:JP2011082271A 公开(公告)日:2011-04-21
- 发明人: SUWADA MAKOTO
- 申请人: Fujitsu Ltd , 富士通株式会社
- 专利权人: Fujitsu Ltd,富士通株式会社
- 当前专利权人: Fujitsu Ltd,富士通株式会社
- 优先权: JP2009231856 2009-10-05
- 主分类号: H05K1/02
- IPC分类号: H05K1/02 ; H05K3/46
摘要:
PROBLEM TO BE SOLVED: To sufficiently reduce impedance fluctuation, propagation delay time fluctuation, and insertion losses that arise when a current flows through a wiring pattern. SOLUTION: A method for manufacturing a wiring board includes a first step of forming a conductive layer on an insulating layer having a glass cloth, a second step of forming a photosensitive resist layer on the conductive layer, a third step of recognizing an origin position of the insulating layer, a fourth step of positioning a mask relative to the origin position, which id so formed as to arrange a wiring pattern only at a position at which the wiring pattern overlaps the glass cloth in a plan view, and disposing the mask on the resist layer, and a fifth step of exposing the resist layer to light via the mask to form the wiring pattern only at the position at which the wiring pattern overlaps the glass cloth in a plan view. COPYRIGHT: (C)2011,JPO&INPIT
摘要(中):
要解决的问题:充分减少电流流过布线图形时产生的阻抗波动,传播延迟时间波动和插入损耗。 解决方案:一种用于制造布线板的方法包括在具有玻璃布的绝缘层上形成导电层的第一步骤,在导电层上形成光敏抗蚀剂层的第二步骤,第三步骤, 绝缘层的起始位置,第四步骤,将掩模相对于原点位置定位,该第一步形成为仅在布置图案与玻璃布重叠的位置在平面图中布置布线图案,并且布置 抗蚀剂层上的掩模,以及通过掩模将抗蚀剂层曝光以形成布线图案的第五步骤,仅在布置图案在平面图中与玻璃布重叠的位置处形成。 版权所有(C)2011,JPO&INPIT
公开/授权文献:
信息查询:
EspacenetIPC结构图谱:
H | 电学 |
--H05 | 其他类目不包含的电技术 |
----H05K | 印刷电路;电设备的外壳或结构零部件;电气元件组件的制造 |
------H05K1/00 | 印刷电路 |
--------H05K1/02 | .零部件 |