![DIFFERENTIAL COMPARATOR CIRCUIT](/ep/2024/06/26/EP4391379A1/abs.jpg.150x150.jpg)
基本信息:
- 专利标题: DIFFERENTIAL COMPARATOR CIRCUIT
- 申请号:EP22306981.6 申请日:2022-12-21
- 公开(公告)号:EP4391379A1 公开(公告)日:2024-06-26
- 发明人: SIMONY, Laurent
- 申请人: STMICROELECTRONICS (GRENOBLE 2) SAS
- 申请人地址: FR 38000 Grenoble 12 Rue Jules Horowitz
- 专利权人: STMICROELECTRONICS (GRENOBLE 2) SAS
- 当前专利权人: STMICROELECTRONICS (GRENOBLE 2) SAS
- 当前专利权人地址: FR 38000 Grenoble 12 Rue Jules Horowitz
- 代理机构: Cabinet Beaumont
- 主分类号: H03K5/24
- IPC分类号: H03K5/24 ; H03M1/56 ; H04N25/75 ; H03F3/00 ; H03F3/45
摘要:
A differential comparator circuit (300) comprising:
- a voltage amplifier (325) of negative gain to receive an analog input signal (VX) and to generate an inverted analog input signal (VXP), wherein the analog input signal (VX) and the inverted analog input signal (VXP) form differential analog input signals; and
- a comparator input circuit (305) comprising:
a first capacitive divider (310) to generate a first signal (INN) as an average of the analog input signal (VX) and a first ramp signal (RMPP);
- a second capacitive divider (320) to generate a second signal (INP) as an average of the inverted analog input signal (VXP) and a second ramp signal (RMPN), wherein the first and second ramp signals (RMPP, RMPN) are differential ramp signals;
the comparator being configured to compare the first (INN) and second signals (INP) to generate a signal transition having a timing based on the input signal (VX).
- a voltage amplifier (325) of negative gain to receive an analog input signal (VX) and to generate an inverted analog input signal (VXP), wherein the analog input signal (VX) and the inverted analog input signal (VXP) form differential analog input signals; and
- a comparator input circuit (305) comprising:
a first capacitive divider (310) to generate a first signal (INN) as an average of the analog input signal (VX) and a first ramp signal (RMPP);
- a second capacitive divider (320) to generate a second signal (INP) as an average of the inverted analog input signal (VXP) and a second ramp signal (RMPN), wherein the first and second ramp signals (RMPP, RMPN) are differential ramp signals;
the comparator being configured to compare the first (INN) and second signals (INP) to generate a signal transition having a timing based on the input signal (VX).