
基本信息:
- 专利标题: EDGE-ALIGNED TEMPLATE STRUCTURE FOR INTEGRATED CIRCUIT PACKAGES
- 申请号:EP22214330.7 申请日:2022-12-16
- 公开(公告)号:EP4203020A1 公开(公告)日:2023-06-28
- 发明人: MALLIK, Debendra , KARHADE, Omkar , AGRAHARAM, Sairam , DESHPANDE, Nitin
- 申请人: INTEL Corporation
- 申请人地址: US Santa Clara, CA 95054 2200 Mission College Blvd.
- 代理机构: 2SPL Patentanwälte PartG mbB
- 优先权: US202117557925 20211221
- 主分类号: H01L23/48
- IPC分类号: H01L23/48 ; H01L25/065 ; H01L23/00
摘要:
Integrated circuit assemblies can be fabricated on a wafer scale, wherein a base template, having a plurality of openings, may cover a base substrate, such as a die wafer, wherein the base substrate has a plurality of first integrated circuit devices formed therein and wherein at least one second integrated circuit device is electrically attached to a corresponding first integrated circuit device through a respective opening in the base template. Thus, when the base substrate and base template are singulated into individual integrated circuit assemblies, the individual integrated circuit assemblies will each have a first integrated circuit that is edge aligned to a singulated portion of the base template. The singulated portion of the base template can provide an improved thermal path, mechanical strength, and/or electrical paths for the individual integrated circuit assemblies.
IPC结构图谱:
H | 电学 |
--H01 | 基本电气元件 |
----H01L | 半导体器件;其他类目未包含的电固体器件 |
------H01L23/00 | 半导体或其他固态器件的零部件 |
--------H01L23/48 | .用于向或自处于工作中的固态物体通电的装置,例如引线、接线端装置 |