Operational instability is prevented without compromising the state transition speed. A mask control circuit (52) is a circuit which generates a mask signal (S7) masking a control signal during a period in which a voltage level of a monitoring target terminal to be monitored is transitioning. The mask control circuit (52) includes: a first input port (52a) which receives a signal supplied to the monitoring target terminal; a second input port (52b) which receives a signal representing the voltage level of the monitoring target terminal; a logic circuit which determines whether the voltage level of the monitoring target terminal is in transition based on signals received from the first input port (52a) and the second input port (52b); and an output port (52c) which outputs a signal indicating a determination result of whether the voltage level of the monitoring target terminal is in transition as the mask signal (S7).