基本信息:
- 专利标题： VIA ARCHITECTURE FOR INCREASED DENSITY INTERFACE
- 申请号：EP18190102.6 申请日：2018-08-21
- 公开(公告)号：EP3462484A1 公开(公告)日：2019-04-03
- 发明人： ALEKSOV, Aleksandar , SARKAR, Arnab , SAIN, Arghya , DARMAWIKARTA, Kristof , BRAUNISCH, Henning , PARMAR, Prashant D. , SHARAN, Sujit , SWAN, Johanna M. , EID, Feras
- 申请人： INTEL Corporation
- 申请人地址： 2200 Mission College Blvd. Santa Clara, CA 95054 US
- 专利权人： INTEL Corporation
- 当前专利权人： INTEL Corporation
- 当前专利权人地址： 2200 Mission College Blvd. Santa Clara, CA 95054 US
- 代理机构： 2SPL Patentanwälte PartG mbB
- 优先权： US201715718012 20170928
- 主分类号： H01L23/522
- IPC分类号： H01L23/522 ; G06F17/50 ; H01L23/528 ; H01L23/66 ; H05K1/02
摘要：
Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.
公开/授权文献:
- EP3462484B1 VIA ARCHITECTURE FOR INCREASED DENSITY INTERFACE 公开/授权日：2021-04-14
IPC结构图谱:
| H | 电学 |
| --H01 | 基本电气元件 |
| ----H01L | 半导体器件；其他类目未包含的电固体器件 |
| ------H01L23/00 | 半导体或其他固态器件的零部件 |
| --------H01L23/34 | .冷却装置；加热装置；通风装置或温度补偿装置 |
| ----------H01L23/522 | ..包含制作在半导体本体上的多层导电的和绝缘的结构的外引互连装置的 |