An amplifier (100) adapted for noise suppression comprises a first input (102) for receiving a first input signal and a second input (104) for receiving a second input signal, the first and second input signals constituting a differential pair. A first output (106) delivers a first output signal and a second output (108) delivers a second output signal, the first and second output signals constituting a differential pair. A first transistor (MCG1) has a first drain (110) coupled to the first output (106) such that all signal current, except parasitic losses, flowing through the first drain (110) flows through the first output (106), and the first transistor (MCG1) further having a first source (112) coupled to the first input (102). A second transistor (MCS1) has a second gate (116) coupled to the first input (102), a second drain (118) coupled to the second output (108) such that all signal current, except parasitic losses, flowing through the second drain (118) flows through the second output (108), and the second transistor (MCS1) further having a second source (120) coupled to a first voltage rail (122). A third transistor (MCS2) has a third gate (124) coupled to the second input (104), a third drain (126) coupled to the first output (106) such that all signal current, except parasitic losses, flowing through the third drain (126) flows through the first output (106), and the third transistor (MCS2) further having a third source (128) coupled to the first voltage rail (122). A fourth transistor (MCG2) has a fourth drain (130) coupled to the second output (108) such that all signal current, except parasitic losses, flowing through the fourth drain (130) flows through the second output (108), and the fourth transistor (MCG2) further having a fourth source (132) coupled to the second input (104). A first load (ZL1) is coupled between the first output (106) and a second voltage rail (136). A second load (ZL2) is coupled between the second output (108) and the second voltage rail (136). A first inductive element (L1) is coupled between the first input (102) and a third voltage rail (138), and a second inductive element (L2) is coupled between the second input (104) and the third voltage rail (138). Transconductance of the first transistor (MCG1) is substantially equal to transconductance of the fourth transistor (MCG2), within ±5%, and transconductance of the second transistor (MCS1) is substantially equal to transconductance of the third transistor (MCS2), within ±5%.