基本信息:
- 专利标题： LLR COMPUTATION DEVICE AND ERROR CORRECTION DECODING DEVICE
- 申请号：EP12852846.0 申请日：2012-10-05
- 公开(公告)号：EP2787706B1 公开(公告)日：2018-05-30
- 发明人： SUGIHARA, Kenya , MATSUMOTO, Wataru
- 申请人： Mitsubishi Electric Corporation
- 申请人地址： 7-3 Marunouchi 2-chome Chiyoda-ku Tokyo 100-8310 JP
- 专利权人： Mitsubishi Electric Corporation
- 当前专利权人： Mitsubishi Electric Corporation
- 当前专利权人地址： 7-3 Marunouchi 2-chome Chiyoda-ku Tokyo 100-8310 JP
- 代理机构： Pfenning, Meinig & Partner mbB
- 优先权： JP2011259068 20111128
- 国际公布： WO2013080668 20130606
- 主分类号： H04L27/00
- IPC分类号： H04L27/00 ; H03M13/25 ; H03M13/39 ; H04L1/00 ; H04L25/06 ; H04L27/38
摘要：
A two-reference-point-pair determining unit 101 determines two reference point pairs by selecting two transmission symbol points with their LLR computation target bit being 0 and two transmission symbol points with their LLR computation target bit being 1. An LLR computation unit 113 assigns weights to the two LLRs calculated for the two reference point pairs, respectively, followed by adding them, and further adds to the addition result a correction term that may be zero sometimes, thus computing LLR for the two reference point pairs.
公开/授权文献:
- EP2787706A1 LLR COMPUTATION DEVICE AND ERROR CORRECTION DECODING DEVICE 公开/授权日：2014-10-08